FIG. 4 is a diagram illustrating a configuration of a processor in a conventional arithmetic processor. In digital signal processor DSP0 illustrated in FIG. 4, control unit CU performs operation control of the entire processor. Control register CR includes a group of registers for controlling operations of the processor, and also includes, for example, a program counter (PC) indicating the location of an instruction executing a program. Program memory PM stores the program as a sequence of instructions, and stores the program in 16 bits×32 words (up to 128 words).
Register file RF includes sixteen 16-bit general-purpose registers R0 to R15 to store variables and constant data to be used during execution of the program.
Arithmetic unit group EU includes divider DIV, multiplier MUL, arithmetic unit ALU, accumulator ACC, and barrel shifter SFT. Divider DIV reads Rn and Rm data in register file RF, and carries out an operation of Rn (16-bit accuracy)/Rm (16-bit accuracy) to 16-bit accuracy×( 1/16-bit accuracy) to 16-bit accuracy×16-bit accuracy to 32-bit accuracy.
Multiplier MUL reads Rn and Rm data in register file RF, and performs multiplication of 16 bits×16 bits to 32 bits. Arithmetic unit ALU carries out an addition operation of 36 bits+36 bits to 36 bits. Accumulator ACC includes a register having a 36-bit length, configured to temporarily store operation results obtained by divider DIV, multiplier MUL and arithmetic unit ALU. Barrel shifter SFT includes 0 to 15 bits, and shifts data from accumulator ACC to the right and stores the shift result in the designated register in register file RF.
The processor thus configured executes an instruction (program) through the following steps.
First, program counter PC shows a program memory address, and an instruction stored in the address is read (fetched) (Step S1). Then, the fetched instruction is decoded (interpreted) (Step S2).
Next, an operation corresponding to the result of the decoding is carried out (Step S3). Thereafter, program counter PC is updated (Step S4). More specifically, in the case of a jump instruction, program counter PC is updated to nextPC in the instruction, or otherwise program counter PC is updated to a value obtained by adding 1 to the value of current program counter PC. Steps S1 to S4 described above are repeated.
FIG. 5 is a diagram illustrating an instruction set held by the processor in the conventional arithmetic processor. In FIG. 5, information on instruction format (Instruction Format), instruction type (Instruction), operation content (Operation) and execution cycle (Exec. Cycle) is recorded in an instruction code table. The instruction format includes information of instruction stop flag (TRIG_WAIT), bit field (TRIG_WHAT), event bit (EVENT), operation code (OPCODE), instruction fieldA (FIELDA) and instruction field B (FIELDB) for 16 bits from the most significant bit MSB (Bit 15) to the least significant bit (Bit 0).
The instruction length is fixed to 16 bits. The operation code (OPCODE) is fixed to 3 bits. Rm/Rn is a 16-bit register designation field, and m, n=0 to 15.
Here, for discussion of problems of the processor, the configuration of the processor and characteristics of the instruction set are described. The processor is categorized as what is termed DSP including a multiplier and a divider. The instruction length is fixed to 16 bits. An operation target is only data stored in the registers as operands and operators.
In the processor having the above configuration, an operand when carrying out an operation (MUL, MAC, DIV) is only register Rn/Rm, and data values cannot be directly referred to as the operation target.
The conventional technology is disclosed in Japanese Patent Application Publication No. 2013-25590.
However, the processor thus configured tends to run short of a data storage area. It is inefficient to allocate the constant data to R0 to R15 that can be used as variables. Operations of constant data and variables are frequently carried out in a target application of the processor, and such data storage area shortage or inefficiency should be addressed.
Generally conceivable methods for avoiding the above problem are to directly specify a constant value in an operand of an operation instruction, and also to specify a memory address where the constant value is stored and read the constant value to be used by the operation instruction from the memory.
However, such methods need to specify the constant value or memory address for the operand. Therefore, the current instruction having the fixed length of 16 bits runs short of the number of bits for designating the operand.
In order to avoid such a situation, it may be possible to extend the instruction length to 24 bits, for example, and specify the constant value or memory address using the extended part. However, such extension of the instruction length increases the program size, and thus increases a required program memory size. Furthermore, there is a problem of lacking compatibility of a previously created program.
Meanwhile, use of variable-length instructions in which the instruction length only for a required instruction is extended can be expected to keep the program size small. However, a fetch of the variable-length instruction needs to involve recognizing of the instruction length of the instruction during decoding of the instruction. As a result, a circuit in a decode unit becomes complex.